Счётчик – делитель на 4,5

// Имя модуля : clk_div_45
// Имя файла : clk_div_45.v
// Функц. назначение : Делитель на 4.5
// Программист : portal-ed.ru
//-----------------------------------------------------
module clk_div_45 (
clk_in, // Входные такты
enable, // Разрешение синхронизации по фронту входящего сигнала
clk_out // Выходные такты
);
// --------------Объявление портов-----------------------
input clk_in ;
input enable ;
output clk_out ;
//--------------Объявление типа портов-------------
wire clk_in ;
wire enable ;
wire clk_out ;
//--------------Внутренние регистры----------------------
reg [3:0] counter1 ;
reg [3:0] counter2 ;
reg toggle1 ;
reg toggle2 ;
//--------------Начало кода-----------------------
always @ (posedge clk_in)
if (enable == 1'b0) begin
counter1 <= 4'b0;
toggle1 <= 0;
end else if ((counter1 == 3 && toggle2) || (~toggle1 && counter1 == 4)) begin
                                                                                                          counter1 <= 4'b0;
                                                                                                          toggle1 <= ~toggle1;
                                                                                                          end else begin
                                                                                                                        counter1 <= counter1 + 1;
                                                                                                                         end
always @ (negedge clk_in)
if (enable == 1'b0) begin
                            counter2 <= 4'b0;
                            toggle2 <= 0;
                            end else if ((counter2 == 3 && ~toggle2) || (toggle2 && counter2 == 4)) begin
                                                                                                                                       counter2 <= 4'b0;
                                                                                                                                       toggle2 <= ~toggle2;
                                                                                                                                       end else begin
                                                                                                                                                     counter2 <= counter2 + 1;
                                                                                                                                                      end
assign clk_out = (counter1 <3 && counter2 < 3) & enable;

endmodule //Конец модуля clk_div_45